Optimizing PCB Layout
This white paper will explore the optimization of PCB layout for an eGaN FET based point of load (POL) buck converter, comparing the conventional designs and proposing a new optimal layout to further reduce parasitics.
The optimal layout will provide improved efficiency, faster switching speeds, and reduced device voltage overshoot compared to conventional designs.
Download this whitepaper to learn more.
Read More
By submitting this form you agree to Efficient Power Conversion Corporation (EPC) contacting you with marketing-related emails or by telephone. You may unsubscribe at any time. Efficient Power Conversion Corporation (EPC) web sites and communications are subject to their Privacy Notice.
By requesting this resource you agree to our terms of use. All data is protected by our Privacy Notice. If you have any further questions please email dataprotection@techpublishhub.com
Related Categories: Capacitors, Power
More resources from Efficient Power Conversion Corporation (EPC)
eGaN® FETs and ICs for 48 V-12 V Regulated Brick Converters
Unregulated performance in a regulated design delivers unprecedented power density.
Low QOSS, zero QRR and low QGD, along with low inductance...
eGaN® FET Drivers and Layout Considerations
When considering gate drive requirements, the three most important parameters for eGaN FETs are (1) the maximum allowable gate voltage, (2) the gat...
Benchmark DC-DC Conversion Efficiency with eGaN FET-Based Buck Converters
For applications requiring high power density and high power, but not requiring electrical isolation, the buck converter has been the workhorse top...