Optimizing PCB Layout
This white paper will explore the optimization of PCB layout for an eGaN FET based point of load (POL) buck converter, comparing the conventional designs and proposing a new optimal layout to further reduce parasitics.
The optimal layout will provide improved efficiency, faster switching speeds, and reduced device voltage overshoot compared to conventional designs.
Download this whitepaper to learn more.
Read More
By submitting this form you agree to Efficient Power Conversion Corporation (EPC) contacting you with marketing-related emails or by telephone. You may unsubscribe at any time. Efficient Power Conversion Corporation (EPC) web sites and communications are subject to their Privacy Notice.
By requesting this resource you agree to our terms of use. All data is protected by our Privacy Notice. If you have any further questions please email dataprotection@techpublishhub.com
Related Categories: Capacitors, Power
More resources from Efficient Power Conversion Corporation (EPC)
Gallium Nitride (GaN) Technology Overview
For over three decades, power management efficiency and cost showed steady improvement as innovations in power MOSFET structures, technology, and c...
Dead-Time Optimization for Maximum Efficiency
In this white paper EPC continues our exploration of optimization issues and look at the impact of dead-time on system efficiency for eGaN® FETs a...
Impact of Parasitics on Performance
With improvements in switching figure of merit provided by eGaN FETs, the packaging and PCB layout parasitics are critical to high performance.
